Integrating AI accelerators in FPGA systems manually can be mundane, repetitive, and error prone, often requiring a detailed understanding of the intricacies of the internals and operation of FPGA devices.
This thesis project involved developing Accelerator Interface Generator (AIG) whose aim was to simplify this process, without the need to manually integrate accelerators into each system. AIG is a configurable and vendor-independent tool designed to integrate any accelerator implementing an AXI4-Stream interface with FPGA DMAs. This resulting accelerator-DMA system can then be incorporated onto a selected FPGA target device, providing a ready-to-use data-processing pipeline that can be utilized both on hardware and in simulation.