The purpose of a Direct Memory Access controller is to arbitrate and handle the transfer of blocks of data directly from an I/O device to the main memory of a system, with minimal intervention of the CPU.
This thesis project was carried out in response to the lack of a portable and vendor-neutral DMA controller. Designed using the flexible Chisel HDL, FastVDMA is now a popular and open source DMA IP: cross-platform and easily adaptable, bringing the engineering freedom that was much needed. Since its release, it has been widely employed in many of Antmicro’s projects e.g. in the Accelerator Interface Generator for performing data I/O operations between a user-defined accelerator and the main memory independently of the CPU.