CPU cache requires careful management to correctly determine what data should be stored across its multiple levels. Depending on hardware configuration and size of cache, and on the memory access patterns in the running software, frequent cache misses can heavily impact the overall performance of the system. In simulation you can analyze cache regardless of the hardware platform, and without changing your software or using a debugger.
This thesis project involved leveraging the existing execution tracing features of the Renode simulation framework to develop a cache modeling analyzer. The tool allows you to gain detailed insights into cache behavior, such as cache hits, misses, and the overall hit ratio, which in turn enables precise analysis of how different cache configurations impact system performance, as well as identification of bottlenecks and opportunities for optimization. Since this mechanism is generic, it can be used in the context of any architecture like ARM or RISC-V during the architectural exploration and early prototyping phase with Renode.